The present invention is related to data conversion, and more particularly to analog to digital converters.
Various analog to digital data converters and conversion techniques have been developed over the years for converting electrical signals from an analog domain to a digital domain. In general, the process of analog to digital conversion includes sampling an analog signal and comparing the sampled analog signal to a threshold value. A binary result is recorded depending upon the result of the comparison. The process of comparing the sample against a threshold may be repeated a number of times with each successive comparison using a different threshold and residue of the sample. The number of iterations typically affects the noise level of any result as well as the resolution of the ultimate digital signal.
Some analog to digital converters rely on delta-sigma modulation techniques. FIG. 1a is a conceptual diagram of a first order delta-sigma analog to digital converter 100. Analog to digital converter 100 includes an operational amplifier 110, a comparator 120, and a counter 130. A positive input of operational amplifier 110 is electrically coupled to ground. A negative input of operational amplifier 110 is electrically coupled to a reference sample capacitor 156 and an input sample capacitor 166. Reference sample capacitor 156 is electrically coupled to a negative version of a voltage reference 150 via a switch 152, and to ground via a switch 154. Input sample capacitor 162 is electrically coupled to a voltage input 160 via a switch 162 and to ground via a switch 164. A feedback capacitor 116 is electrically coupled between the output and the negative input of operational amplifier 110 by way of a switch 114. Another switch 112 allows for shorting the output of operational amplifier 110 to the negative input thereof.
In operation, voltage input 160 is sampled by closing switch 162 and switch 112. This allows input sample capacitor 166 to be charged to a level reflecting voltage input 160. The charge from input sample capacitor 166 is then transferred to feedback capacitor 116 by opening switch 162 and switch 112, and closing switch 114 and switch 164. This results in an output from operational amplifier 110 at the input of comparator 120. Where the gain of operational amplifier 110 is unity, the output is approximately equal to voltage input 160. The output is compared with voltage reference 150. Where the result is a logic ‘0’, counter 130 is not incremented. In the next pass, voltage input 160 is again sampled by closing switch 162 and switch 112. Once charging is complete, charge is transferred from capacitor 166 to capacitor 116 by closing switch 114 and switch 164. This results in a value of approximately double voltage input 160 at the output of operational amplifier 110. Again, where the result is a logic ‘0’, counter 130 is not incremented and substantially the same process is repeated until the result of a logic ‘1’ is achieved.
Alternatively, on any pass where the result of the comparison is a logic ‘1’, counter 130 is incremented. Further, where the result is a logic ‘1’, the negative version of the voltage reference 150 is sampled along with voltage input 160 on the next pass. This is done by closing switch 152, switch 162 and switch 112. This causes charge to build up on reference sample capacitor 156 representing the negative reference voltage, and charge to build up on input sample capacitor 166 representing input voltage 160. The charge from both of the aforementioned capacitors is transferred to feedback capacitor 116 by closing switch 114, switch 154 and switch 164. By continually re-sampling input voltage 160 and sampling the negative voltage reference any time a logic ‘1’ is noted, the following residue will remain for a counter value of X and a number of iterations N:Residue=NVin−XVref.The digital value representing the voltage input is that maintained on counter 130 at the end of the process. The process may be continued for a large number of iterations which would result in a progressively finer resolution. Unfortunately, the number of samples (N) to create a defined output resolution of ADC result 140 increases exponentially. For example, for a ten bit resolution one thousand, twenty-four (210) samples are required. In comparison, for a twenty bit resolution, over one million samples are required (220). Thus, while analog to digital converter 100 is capable of providing accurate results, results exhibiting relatively high resolution require substantial conversion time.
Other approaches for analog to digital conversion exist. Turning to FIG. 1b, a conceptual diagram of a SAR based analog to digital converter 170 is shown. As shown, SAR based analog to digital converter 170 includes a comparator 175 and a shift register 185 that provides an ADC result 190. In operation, a voltage input 180 is compared with one half of a voltage reference 194. Where the voltage input is greater than one half of the voltage reference 194, a logic ‘1’ is shifted into shift register 185. Alternatively, where the voltage input is less than one half of the voltage reference 194, a logic ‘0’ is shifted into shift register 185.
Next, where the previous comparison indicated that voltage input 180 is greater than one half of the voltage reference 194, voltage input 180 is compared with one half of the voltage reference 194 augmented with one quarter of the voltage reference 196 by an adder 172 (i.e., voltage input 180 is compared with three quarters of the voltage reference). Again, where the comparison indicates a greater than condition, a logic ‘1’ is shifted into shift register 185. In contrast, where the comparison indicates a less than condition, a logic ‘0’ is shifted into shift register 185.
Alternatively, where the previous comparison indicated that voltage input 180 is less than one half of the voltage reference 194, voltage input 180 is compared with one half of the voltage reference 194 decremented by one quarter of the voltage reference 196 by an adder 172 (i.e., voltage input 180 is compared with one quarter of the voltage reference). Again, where the comparison indicates a greater than condition, a logic ‘1’ is shifted into shift register 185. In contrast, where the comparison indicates a less than condition, a logic ‘0’ is shifted into shift register 185. This process is continued for lower order multiples of the voltage reference. As will be appreciated, the aforementioned process is capable of providing ADC result 190 with a very high resolution in a relatively small amount of time. In particular, only a single iteration is required to produce each bit of resolution. For example, for a ten bit resolution ten iterations are required, and for twenty bits of resolution only twenty iterations are required. Thus, while analog to digital converter 170 is capable of providing quick results, the results are often inaccurate due to noise.
Thus, for at least the aforementioned reasons, there exists a need in the art for advanced systems and devices for analog to digital conversion.